Certain Central Processing Unit (CPU) management methods have been devised. For example, U.S. Pat. Pub. 2009/0265572 (the disclosure of which is hereby incorporated by reference) describes a method for performing a CPU soft start, the method including controlling the voltage of a power supply to match a specific frequency. U.S. Pat. Pub. 2004/0221287 (the disclosure of which is hereby incorporated by reference) also describes a method for performing a CPU soft start, the method including controlling different clock sources used in low power and normal operation states. U.S. Pat. No. 7,219,245 (the disclosure of which is hereby incorporated by reference) describes a method for adapting CPU frequency based on idleness and types of instructions to be executed. U.S. Pat. No. 6,564,328 (the disclosure of which is hereby incorporated by reference) describes method for controlling CPU temperature by regulating frequency based on a power consumption estimation. U.S. Pat. Pub. 2009/0259869 (the disclosure of which is hereby incorporated by reference) describes a method for estimating the power consumption of a processing core. U.S. Pat. Pub. 2009/0089598 (the disclosure of which is hereby incorporated by reference) and U.S. Pat. Pub. 2005/0132238 (the disclosure of which is hereby incorporated by reference) describe methods for adjusting processor frequency based on hardware feedback, processor stall, instructions, thread level run time, etc. However, CPU power supply integrity is not considered as a concern in these cited documents.
The performance of CPUs on integrated circuits is tightly connected to the CPU power supply integrity. For each operating frequency there is a threshold operating voltage that should hopefully be sustained to help ensure correct operation. The more noise that is present on the power supply, the larger the margin is to be used for the nominal voltage versus the minimum operating voltage in order to ensure the threshold operating voltage is met.
In general, the largest source for noise on the CPU power supply is the variations on the current drawn by the CPU itself. Two methods may help mitigate the effects of these variations.
A first method involves the use of special analog circuitry to detect low levels on the CPU supply voltage, and modify the operating frequency of the CPU to mitigate the low supply voltage level, as well as reduce the supply voltage required for correct operation. However, this method is complicated to implement and depends on analog functionality being developed for every process node.
A second method involves the use of software to control the operating frequency for the CPU when transitioning to and from an idle state. Transitions to and from an idle state can cause sharp changes in the current consumed by the CPU, and are typically the worst case for noise on the power supply. However, this method is complicated to implement with full efficiency, because it is difficult for software to cover the different possible ways to enter and exit idle state, especially for multi-core CPUs.
Embodiments of the disclosure described herein will improve the situation.